1. Field of the Invention
The present invention relates to a quartz oscillation circuit and quartz oscillation integrated circuit device.
2. Description of the Related Art
The conventional CMOS oscillation circuit is formed, as shown in FIG. 10, by a quartz oscillator X1 connected between input and output terminals of a CMOS inverter X2, and a feedback resistor X3 connected between these input and output terminals. Furthermore, these input terminal and output terminal are respectively connected through capacitance elements X4 and X5 to a power supply VSS (0 V).
Recently, in such oscillation circuits miniaturization in quartz oscillator has been advanced due to a requirement to reduce overall quartz oscillation module sizes and increase operation frequency speeds. However, it becomes impossible to think light of the problem of quartz current (current flowing through quartz upon oscillation) caused by reducing the size in the quartz oscillator. For example, increased amplitude due to excessive quartz current induces frequency instability, leading to breakage of the quartz oscillator in a worst case.
In an attempt to solve such a problem, there is filed an patent application as Japanese Patent Application No. H9-5765 (xe2x80x9cQuartz Oscillation Circuit and Quartz Oscillation Integrated Circuit Devicexe2x80x9d) published Aug. 7, 1998 and corresponding to U.S. patent application Ser. No. 09/004,686, filed Jan. 8, 1998 by the present applicant and inventor. This is provided, for example as shown in FIG. 11, with a resistor Y1 between a capacitance element X4 and a power supply terminal VDD, and a resistor Y2 between a capacitance element X5 and the power supply terminal VDD, in order to reduce a quartz current.
It has been discussed in the earlier patent application that the value of the resistance Y1, Y2 is preferably determined from a balance between a negative resistance and a quartz current. However, there has been a desire to concretely determine an optimum range.
The present invention has obtained an optimum range as desired above through further studies conducted after filing the earlier patent application.
The present invention has determined a sum of values of resistances provided between a CMOS inverter input terminal and power supply terminal and/or between an output terminal and power supply terminal in a range of from 10xcexa9 to 320xcexa9.
A quartz oscillation circuit according to the present invention comprises: a CMOS inverter; a quartz oscillator connected between input and output terminals of the CMOS inverter; a feedback resistor connected between the input and output terminals of the CMOS inverter; a first capacitance element provided between a first connection point of the input terminal of the CMOS inverter and the quartz oscillator and a power supply terminal having a particular potential; a second capacitance element provided between a second connection point of the output terminal of the CMOS inverter and the quartz oscillator and the particular potential power supply terminal; and resistors provided at any one or a plurality of points of between the first connection point and the first capacitance element, between the second connection point and the second capacitance element and between the second capacitance element and the power supply terminal; wherein a sum of resistance values of the resistors lies in a range of from 10xcexa9 to 320xcexa9.
A quartz oscillation integrated circuit device according to the present invention comprises: a CMOS inverter; terminals for connecting a quartz oscillator between input and output terminals of the CMOS inverter; a feedback resistor connected between the input and output terminals of the CMOS inverter; a first capacitance element provided between a first connection point of the input terminal of the CMOS inverter and the quartz oscillator and a power supply terminal having a particular potential; a second capacitance element provided between a second connection point of the output terminal of the CMOS inverter and the quartz oscillator and the particular potential power supply terminal; and resistors provided at any one or a plurality of points of between the first connection point and the first capacitance element, between the second connection point and the second capacitance element and between the second capacitance element and the power supply terminal; wherein a sum of resistance values of the resistors lies in a range of from 10xcexa9 to 320xcexa9.